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TPS79501QDRBRQ1 Datasheet Preview

TPS79501QDRBRQ1 Datasheet

LOW-DROPOUT LINEAR REGULATOR

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TPS79501-Q1
www.ti.com
ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 500-mA
LOW-DROPOUT LINEAR REGULATORS
Check for Samples: TPS79501-Q1
SLVSAJ9 – SEPTEMBER 2010
FEATURES
1
2 Qualified for Automotive Applications
• 500-mA Low-Dropout Regulator With Enable
• High PSRR (50 dB at 10 kHz)
• Ultralow Noise (33 mVRMS, TPS79501-Q1)
• Fast Start-Up Time (50 ms)
• Stable With a 1-mF Ceramic Capacitor
• Excellent Load/Line Transient Response
• Low Dropout Voltage (110 mV at Full Load,
TPS79501-Q1)
APPLICATIONS
• RF: VCOs, Receivers, ADCs
• Audio
• Bluetooth®, Wireless LAN
DESCRIPTION
The TPS79501-Q1 low-dropout (LDO), low-power
linear voltage regulator features high power-supply
rejection ratio (PSRR), ultralow noise, fast start-up,
and excellent line and load transient responses in a
small outline SON package. The device is stable with
a small 1-mF ceramic capacitor on the output. The
TPS79501-Q1 uses an advanced, proprietary
BiCMOS fabrication process to yield extremely low
dropout voltages (for example, 110 mV at 500 mA).
The device achieves fast start-up times
(approximately 50 ms with a 0.001-mF bypass
capacitor) while consuming very low quiescent
current (265 mA, typical). Moreover, when the device
is placed in standby mode, the supply current is
reduced to less than 1 mA. The TPS79501-Q1
exhibits approximately 33 mVRMS of output voltage
noise at 3-V output with a 0.1-mF bypass capacitor.
Applications with analog components that are
noise-sensitive, such as portable RF electronics,
benefit from the high-PSRR and low-noise features,
as well as from the fast response time.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated




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TPS79501QDRBRQ1 Datasheet Preview

TPS79501QDRBRQ1 Datasheet

LOW-DROPOUT LINEAR REGULATOR

No Preview Available !

TPS79501-Q1
SLVSAJ9 – SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TA
-40°C to 125°C
SON – DRB
ORDERING INFORMATION(1)
PACKAGE
ORDERABLE
Tape and reel
TPS79501QDRBRQ1
TOP-SIDE MARKING
QVE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating temperature (unless otherwise noted)(1)
VIN range
VEN range
VOUT range
Peak output current
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range, Tstg
VALUE
–0.3 V to 6 V
–0.3 V to VIN + 0.3 V
6V
Internally limited
See the Thermal Information Table
–40°C to 150°C
–65°C to 150°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL INFORMATION
THERMAL METRIC(1)(2)
qJA
qJCtop
qJB
yJT
yJB
qJCbot
Junction-to-ambient thermal resistance(4)
Junction-to-case (top) thermal resistance(5)
Junction-to-board thermal resistance(6)
Junction-to-top characterization parameter(7)
Junction-to-board characterization parameter(8)
Junction-to-case (bottom) thermal resistance(9)
TPS795xx (3)
DRB (8 PINS)
47.8
83
n/a
2.1
17.8
12.1
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the RGW and DRC packages are derived by thermal simulations based on JEDEC-standard methodology as specified
in the JESD51 series. The following assumptions are used in the simulations:
(a) DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
(b) DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2
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Copyright © 2010, Texas Instruments Incorporated


Part Number TPS79501QDRBRQ1
Description LOW-DROPOUT LINEAR REGULATOR
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