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TPS7A8300 Datasheet Preview

TPS7A8300 Datasheet

LDO Voltage Regulator

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TPS7A8300
SBVS197F – MAY 2013 – REVISED OCTOBER 2015
TPS7A8300 2-A, 6-µVRMS, RF, LDO Voltage Regulator
1 Features
1 Ultralow Dropout: 125 mV Maximum at 2 A
• Output Voltage Noise: 6 µVRMS
• Power-Supply Ripple Rejection:
– 40 dB at 1 MHz
• Input Voltage Range:
– Without BIAS: 1.4 V to 6.5 V
– With BIAS: 1.1 V to 6.5 V
• Two Output Voltage Modes:
– ANY-OUT™ Version (User-Programmable
Output via PCB Layout):
– No External Resistor Required
– Output Voltage Range: 0.8 V to 3.95 V
– Adjustable Version:
– Output Voltage Range: 0.8 V to 5.0 V
• 1.0% Accuracy Over Line, Load, and Temperature
• Stable with a 22-µF Output Ceramic Capacitor
• Programmable Soft-Start Output
• Power-Good (PG) Output
• Available Packages:
– 5-mm × 5-mm VQFN-20
– 3.5-mm × 3.5-mm VQFN-20
2 Applications
• RF, IF Components: VCO, ADC, DAC, LVDS
• Wireless Infrastructure: SerDes, FPGA, DSP™
• Test and Measurement
• Instrumentation, Medical, and Audio
Application Example
TPS7A8300
RF LDO
3 Description
The TPS7A8300 is a low-noise (6 µVRMS), low-
dropout voltage regulator (LDO) capable of sourcing
a 2-A load with only 125 mV of maximum dropout.
The TPS7A8300 output voltages are fully user-
adjustable (up to 3.95 V) using a printed circuit board
(PCB) layout without the need of external resistors,
thus reducing overall component count. For higher
output voltage applications, the device achieves
output voltages up to 5 V with the use of external
resistors. The device supports very low input voltages
(down to 1.1 V) with the use of an additional BIAS
rail.
With very high accuracy (1% over line, load, and
temperature), remote sensing, and soft-start
capabilities to reduce inrush current, the TPS7A8300
is ideal for powering high-current, low-voltage devices
such as high-end microprocessors and field-
programmable gate arrays (FPGAs).
The TPS7A8300 is designed to power-up noise-
sensitive components in high-speed communication
applications. The very low-noise, 6-µVRMS device
output and high broad-bandwidth PSRR (40 dB at
1 MHz) minimizes phase noise and clock jitter in
high-frequency signals. These features maximize
performance of clocking devices, analog-to-digital
converters (ADCs), and digital-to-analog converters
(DACs).
For applications where positive and negative low-
noise rails are required, consider TI's TPS7A33 family
of negative high-voltage, ultralow-noise linear
regulators.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS7A8300
VQFN (20)
VQFN (20)
5.00 mm × 5.00 mm
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Amplifier
TPS7A33
Negative-Voltage
Regulator
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




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TPS7A8300 Datasheet Preview

TPS7A8300 Datasheet

LDO Voltage Regulator

No Preview Available !

TPS7A8300
SBVS197F – MAY 2013 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configurations and Functions ....................... 4
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics.......................................... 6
6.6 Typical Characteristics .............................................. 8
7 Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 24
8 Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application .................................................. 29
8.3 Do's and Don'ts ....................................................... 31
9 Power-Supply Recommendations...................... 31
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 33
11.1 Device Support...................................................... 33
11.2 Documentation Support ........................................ 33
11.3 Community Resources.......................................... 33
11.4 Trademarks ........................................................... 33
11.5 Electrostatic Discharge Caution ............................ 34
11.6 Glossary ................................................................ 34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2014) to Revision F
Page
• Added title to page 1 graphic ................................................................................................................................................. 1
• Updated ESD Ratings table to current standards ................................................................................................................. 5
• Changed Figure 52: changed connection of EN pin ........................................................................................................... 21
• Changed Enable (EN) and Undervoltage Lockout (UVLO) section: updated wording for better clarity on use of the
Enable (EN) pin ................................................................................................................................................................... 25
Changes from Revision D (February 2013) to Revision E
Page
• Changed format to meet latest data sheet standards; added new sections, and moved existing sections........................... 1
• Changed first ANY-OUT sub-bullet of fifth Features bullet ................................................................................................... 1
• Changed eighth Features bullet: broke Soft-Start Output and PG Output into two separate Features bullets .................... 1
• Changed first sentence of second paragraph in Description section .................................................................................... 1
• Changed RGW and RGR drawings: removed spacing between number and unit in pins 5 to 7 and 9 to 11 ...................... 4
• Changed first row of Pin Functions table: deleted spacing between number and unit in pin names..................................... 4
• Added capacitor value to BIAS pin description in Pin Functions table................................................................................... 4
• Changed 87% to 89% in the PG pin description of the Pin Functions table .......................................................................... 4
• Changed thermal pad description in Pin Functions table ....................................................................................................... 4
• Changed conditions statements for Absolute Maximum Ratings and Recommended Operating Conditions tables ............ 5
• Added Recommended Operating Conditions table ................................................................................................................ 5
• Changed the Typical Characteristics section: changed all curve titles and conditions ......................................................... 8
• Changed title of Figure 11 ..................................................................................................................................................... 8
• Added Overview section ...................................................................................................................................................... 17
• Changed second paragraph of Overview section: changed that can be groups, as follows to including ........................... 17
• Changed functional block diagram footnote ......................................................................................................................... 17
• Added Feature Description section ...................................................................................................................................... 18
• Changed adjustable version to adjustable configuration in first paragraph of Adjustable Operation section ..................... 19
2 Submit Documentation Feedback
Product Folder Links: TPS7A8300
Copyright © 2013–2015, Texas Instruments Incorporated


Part Number TPS7A8300
Description LDO Voltage Regulator
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