TSB41AB3-EP Datasheet | Texas Instruments

in Battery Powered Applications Include: Automatic Device Power Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down D Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz D Interface to Link Layer Controller Supports Low-Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation D Interoperable With Link-Layer Controllers Using 3.3-V and 5-V Supplies D Interoperable With Other Physical Layers (PHYs) Using 3.3-V and 5-V Supplies D Low Cost 24.576-MHz Crystal Provides Transmit Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz D Separate Cable Bias (TPBIAS) for Each Port D Single 3.3-V Supply Operation D Low-Cost High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package D Direct Drop-In Upgrade for TSB41LV03APFP and TSB41LV03PFP D Software Device Reset (SWR) D Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB41AB3 Does Not Load the TPBIAS of Any Connected Device and Blocks Any Leakage From the Port Back to Power Plane D The TSB41AB3 Has a 1394a pliant mon-Mode Noise Filter on the Ining Bias Detect Circuit to Filter Out Cross-Talk Noise Please be aware that an important notice...