TSB41LV04A Datasheet | Texas Instruments

Features to Conserve Energy in Battery-Powered Applications Include: Automatic Device Power-Down during Suspend, Device Power-Down Terminal, Link Interface Disable Via LPS, and Inactive Ports Powered-Down D Ultra Low-Power Sleep Mode D Node Power Class Information Signaling for System Power Management D Cable Power Presence Monitoring D Cable Ports Monitor Line Conditions for Active Connection to Remote Node SLLS379 - OCTOBER 1999 D Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit and P1394a Features D Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz D Interface to Link-Layer Controller Supports Low-Cost TITMBus-Holder Isolation and Optional Annex J Electrical Isolation D Interoperable With Link-Layer Controllers Using 3.3-V and 5-V Supplies D Interoperable With Other Physical Layers (PHYs) Using 3.3-V and 5-V Supplies D Low-Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz D Ining Data Resynchronized to Local Clock D Logic Performs System Initialization and Arbitration Functions D Encode and Decode Functions Included for Data-Strobe Bit Level Encoding D Separate Cable Bias (TPBIAS) for Each Port D Single 3.3-V Supply Operation D Low-Cost High-Performance 80-Pin TQFP (PFP) Thermally Enhanced Package description The TSB41LV04A provides the digital and analog transceiver functions needed to implement a four-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV04A is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. Please be aware that an important notice...