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UCC21520A-Q1 Datasheet Preview

UCC21520A-Q1 Datasheet

Dual-Channel Gate Driver

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UCC21520-Q1
UCC21520A-Q1
SLUSCQ2C – OCTOBER 2017 – REVISED MARCH 2020
UCC21520-Q1, UCC21520A-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver
for Automotive
1 Features
1 Qualified for automotive applications
• AEC-Q100 qualified with the following results
– Device temperature grade 1
– Device HBM ESD classification level H2
– Device CDM ESD classification level C6
• Universal: dual low-side, dual high-side or half-
bridge driver
• Operating temperature range –40 to +125°C
• Switching parameters:
– 19-ns typical propagation delay
– 10-ns minimum pulse width
– 5-ns maximum delay matching
– 6-ns maximum pulse-width distortion
• Common-mode transient immunity (CMTI) greater
than 100 V/ns
• Surge Immunity up to 12.8 kV
• Isolation barrier life >40 Years
• 4-A peak source, 6-A peak sink output
• TTL and CMOS compatible inputs
• 3-V to 18-V input VCCI range to interface with
both digital and analog controllers
• Up to 25-V VDD output drive supply
– 5-V and 8-V VDD UVLO options
• Programmable overlap and dead time
• Rejects input pulses and noise transients shorter
than 5 ns
• Fast disable for power sequencing
• Safety-related certifications:
– 8000-VPK Reinforced Isolation per DIN V VDE
V 0884-11:2017-01
– 5.7-kVRMS Isolation for 1 minute per UL 1577
– CSA Certification per IEC 60950-1, IEC 62368-
1, IEC 61010-1 and IEC 60601-1 End
Equipment Standards
– CQC certification per GB4943.1-2011
2 Applications
• HEV and BEV Battery Chargers
• Isolated Converters in DC-DC and AC-DC Power
Supplies
• Motor Drive and DC-to-AC Solar Inverters
• Uninterruptible Power Supply (UPS)
3 Description
The UCC21520-Q1 is an isolated dual-channel gate
drivers with 4-A source and 6-A sink peak current. It
is designed to drive power MOSFETs, IGBTs, and
SiC MOSFETs up to 5-MHz with best-in-class
propagation delay and pulse-width distortion.
The input side is isolated from the two output drivers
by a 5.7-kVRMS reinforced isolation barrier, with a
minimum of 100-V/ns common-mode transient
immunity (CMTI). Internal functional isolation between
the two secondary-side drivers allows a working
voltage of up to 1500 VDC.
Every driver can be configured as two low-side
drivers, two high-side drivers, or a half-bridge driver
with programmable dead time (DT). A disable pin
shuts down both outputs simultaneously, and allows
normal operation when left open or grounded. As a
fail-safe measure, primary-side logic failures force
both outputs low.
Each device accepts VDD supply voltages up to 25
V. A wide input VCCI range from 3 V to 18 V makes
the driver suitable for interfacing with both analog and
digital controllers. All supply voltage pins have under
voltage lock-out (UVLO) protection.
With all these advanced features, the UCC21520-Q1
enables high efficiency, high power density, and
robustness.
Device Comparison(1)
PART NUMBER
PACKAGE
UVLO Level
UCC21520-Q1
DW SOIC (16)
8V
UCC21520A-Q1
DW SOIC (16)
5V
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VCCI 3,8
INA 1
DIS 5
NC 7
DT 6
INB 2
GND 4
MOD
Disable,
UVLO
and
Deadtime
MOD
Driver
DEMOD UVLO
16 VDDA
15 OUTA
14 VSSA
Functional Isolation
13 NC
12 NC
Driver
DEMOD UVLO
11 VDDB
10 OUTB
9 VSSB
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




etcTI

UCC21520A-Q1 Datasheet Preview

UCC21520A-Q1 Datasheet

Dual-Channel Gate Driver

No Preview Available !

UCC21520-Q1
UCC21520A-Q1
SLUSCQ2C – OCTOBER 2017 – REVISED MARCH 2020
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 6
6.5 Power Ratings........................................................... 6
6.6 Insulation Specifications............................................ 7
6.7 Safety-Related Certifications..................................... 8
6.8 Safety-Limiting Values .............................................. 8
6.9 Electrical Characteristics........................................... 9
6.10 Switching Characteristics ...................................... 10
6.11 Insulation Characteristics Curves ......................... 11
6.12 Typical Characteristics .......................................... 12
7 Parameter Measurement Information ................ 16
7.1 Propagation Delay and Pulse Width Distortion....... 16
7.2 Rising and Falling Time ......................................... 16
7.3 Input and Disable Response Time.......................... 16
7.4 Programable Dead Time ........................................ 17
7.5 Power-up UVLO Delay to OUTPUT........................ 17
7.6 CMTI Testing........................................................... 18
8 Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 24
9 Application and Implementation ........................ 27
9.1 Application Information............................................ 27
9.2 Typical Application .................................................. 27
10 Power Supply Recommendations ..................... 39
11 Layout................................................................... 40
11.1 Layout Guidelines ................................................. 40
11.2 Layout Example .................................................... 41
12 Device and Documentation Support ................. 43
12.1 Documentation Support ....................................... 43
12.2 Certifications ......................................................... 43
12.3 Receiving Notification of Documentation Updates 43
12.4 Community Resources.......................................... 43
12.5 Trademarks ........................................................... 43
12.6 Electrostatic Discharge Caution ............................ 43
12.7 Glossary ................................................................ 43
13 Mechanical, Packaging, and Orderable
Information ........................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2018) to Revision C
Page
• Changed DT pin description .................................................................................................................................................. 4
• Added cross reference to table note 1 .................................................................................................................................. 5
• Added VDDx power-up delay typ and max values .............................................................................................................. 10
• Changed DT pin configuration recommendations ............................................................................................................... 25
• Added update to bootstrap circuit recommendations .......................................................................................................... 28
• Added update to gate resistor selection recommendations ................................................................................................ 30
• Added gate to source resistor recommendation .................................................................................................................. 30
• Added update to Cboot selection recommendations ........................................................................................................... 32
Changes from Revision A (May 2018) to Revision B
Page
• Changed UCC21520A-Q1 Advance Information marketing status to initial release. ............................................................. 1
• Added detailed description for DISABLE Pin and DT Pin ...................................................................................................... 4
• Changed tPWD in the switching characteristic section. .......................................................................................................... 10
• Added feature descriptions for UVLO delay to OUTPUT .................................................................................................... 17
• Added bullet "It is recommended..." bullet to the component placement in the Layout Guidelines. ................................... 40
2 Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: UCC21520-Q1 UCC21520A-Q1


Part Number UCC21520A-Q1
Description Dual-Channel Gate Driver
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