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UCD7232 Datasheet Preview

UCD7232 Datasheet

Digital Control Compatible Synchronous-Buck Gate Driver

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UCD7232
www.ti.com
SLUSAH3 MAY 2011
Digital Control Compatible Synchronous-Buck Gate Driver
With Current Sense and Fault Protection
Check for Samples: UCD7232
FEATURES
1
Dual High Current Drivers.
Full Compatibility with TI Fusion Digital Power
Supply Controllers, such as UCD91xx and
UCD92xx Families
Operational to 2 MHz Switching Frequency
High-Side FET and Output Current Limit
Protection with Independently Adjustable
Thresholds
Fast High-Side Overcurrent Sense Circuit with
Fault Flag Output Prevents Catastrophic
Current Levels on a Cycle-by-Cycle Basis
Differential High-Gain Current Sense Amplifier
Voltage Proportional to Load Current Monitor
Output
Wide Input Voltage Range: 4.7 V to 15 V
Operation to 2.2 V Input Supported with an
External 4.5-6.5 V Bias Supply
Onboard Regulated Supplies for Gate Drive
and Internal Circuits
Integrated Thermal Shutdown
Selectable Operation Modes:
PWM plus Synchronous Rectifier Enable
(SRE) with Automatic Dead-Time Control
Direct High-Gate and Low-Gate Inputs for
Direct FET Control
3-State PWM Input for Power Stage Shutdown
UVLO Housekeeping Circuit
Rated from 40°C to +125°C Junction
Temperature
APPLICATIONS
Digitally-Controlled Synchronous-Buck Power
Stages for Single- and Multi-Phase
Applications
Digitally-Controlled Power Modules
DESCRIPTION
The UCD7232 high current driver is specifically
designed for digitally-controlled, point-of-load,
synchronous buck switching power supplies. Two
driver circuits provide high charge and discharge
current for the high-side NMOS switch and the
low-side NMOS synchronous rectifier in a
synchronous buck circuit. The MOSFET gates are
driven by an internally regulated VGG supply. The
internal VGG regulator can be disabled to permit the
user to supply their own gate drive voltage. This
flexibility allows a wide power conversion input
voltage range of 2.2 to 15 V. Internal under voltage
lockout (UVLO) logic insures VGG is good before
allowing chip operation.
A drive logic block allows operation in one of two
modes selected by the SRE Mode pin. In
Synchronous Mode, the logic block uses the PWM
signal to control both the high-side and low-side gate
drive signals. Dead time is automatically adjusted to
prevent cross conduction. The Synchronous Rectifier
Enable (SRE) pin controls whether or not the low-side
FET is turned on when the PWM signal is low. In
Independent Mode, the PWM and SRE pins control
the high-side and low-side gates directly. No
anti-cross-conduction logic is used in this mode.
On-board comparators monitor the voltage across the
high side switch and the voltage across an external
current sense element to safeguard the power stage
from sudden high current loads. Blanking delay is set
for the high side comparator by a single resistor in
order to avoid false reports coincident with switching
edge noise. In the event of a high-side fault or an
over-current fault, the high-side FET turned off and
the Fault Flag (FLT) is asserted to alert the digital
controller. The fault thresholds are independently set
by the HS Sense and ILIM pins.
Output current is measured and monitored by a
precision, high gain, switched capacitor differential
amplifier that processes the voltage present across
an external current sense element. The amplified
signal is available for use by the digital controller on
the IMON pin. The current sense amplifier has output
offset of 0.5 V so that both positive (sourcing) and
negative (sinking) current can be sensed.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated




etcTI

UCD7232 Datasheet Preview

UCD7232 Datasheet

Digital Control Compatible Synchronous-Buck Gate Driver

No Preview Available !

UCD7232
SLUSAH3 MAY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
An on-chip temperature sense monitors the die temperature. If it exceeds approximately 165°C, the temperature
sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. The temperature fault
automatically clears when the die temperatures falls by approximately 20°.
FUNCTIONAL BLOCK DIAGRAM
VGG DIS
13
PWM
10
SRE
4
SRE Mode
3
FLT
2
UCD7232
Digital Control
9
16
BP3
Vin
Bias + VGG
Generator
UVLO
HS Fault
RDLY
11
Blanking
Control
TSD OC Fault
ILIM
5
Thermal
Sense
HS Sense
1
BST
18
HS Gate
19
SW
20
VGG
17
LS Gate
15
PGND
14
IMON
6
0.5 V
G = 50
CSP
8
CSN
7
AGND
12
PAD
PP
Figure 1. UCD7232 Block Diagram
2
Copyright © 2011, Texas Instruments Incorporated


Part Number UCD7232
Description Digital Control Compatible Synchronous-Buck Gate Driver
Maker etcTI
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