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74ABT00PW Datasheet Preview

74ABT00PW Datasheet

Quad 2-input NAND gate

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74ABT00
Quad 2-input NAND gate
Rev. 4 — 5 October 2020
Product data sheet
1. General description
The 74ABT00 is a quad 2-input NAND gate. This device is fully specified for partial power down
applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
2. Features and benefits
Supply voltage range from 4.5 V to 5.5 V
BiCMOS high speed and output drive
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74ABT00D
-40 °C to +85 °C
SO14
74ABT00PW
-40 °C to +85 °C
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
4. Functional diagram
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
mna212
Fig. 1. Logic symbol
1
2
&
3
4
5
&
6
9
10
&
8
12
13
&
11
mna246
Fig. 2. IEC logic symbol
A
Y
B
mna211
Fig. 3. Logic diagram (one gate)




nexperia

74ABT00PW Datasheet Preview

74ABT00PW Datasheet

Quad 2-input NAND gate

No Preview Available !

Nexperia
5. Pinning information
74ABT00
Quad 2-input NAND gate
5.1. Pinning
74ABT00
1A 1
1B 2
14 VCC
13 4B
1Y 3
12 4A
2A 4
11 4Y
2B 5
10 3B
2Y 6
9 3A
GND 7
8 3Y
aaa-024190
Fig. 4. Pin configuration for SOT108-1 (SO14)
74ABT00
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
aaa-024191
Fig. 5. Pin configuration for SOT402-1 (TSSOP14)
5.2. Pin description
Table 2. Pin description
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
VCC
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input
nA
nB
L
X
X
L
H
H
Description
data input
data input
data output
ground (0 V)
supply voltage
Output
nY
H
H
L
74ABT00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 5 October 2020
© Nexperia B.V. 2020. All rights reserved
2 / 10


Part Number 74ABT00PW
Description Quad 2-input NAND gate
Maker nexperia
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