74AHC257 Datasheet | Nexperia

description The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 7-A. The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and are controlled by a mon data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. The 74AHC257; 74AHCT257 is the logic implementation of a 4-pole 2-position switch, where the position of the switch is determined by the logic levels applied to input S. The outputs are forced to a high-impedance OFF-state when OE is HIGH. The logic equations for the outputs are: 1Y = OE × (1I1 × S + 1I0 × S) 2Y = OE × (2I1 × S + 2I0 × S) 3Y = OE × (3I1 × S + 3I0 × S) 4Y = OE × (4I1 × S + 4I0 × S) The 74AHC257; 74AHCT257 is identical to the 74AHC258; 74AHCT258, but has non-inverting (true) outputs. 2. Features I Balanced propagation delays I All inputs have Schmitt-trigger actions I Non-inverting data path I Inputs accept voltages higher than VCC I Input levels: N For 74AHC257: CMOS level N For 74AHCT257: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from - 40 °C to +85 °C and from - 40 °C to +125 °C Nexperia 74AHC257; 74AHCT257 Quad 2-input multiplexer; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC257D - 40 °C to +125 °C SO16 74AHC257PW - 40 °C to +125 °C TSSOP16 74AHCT257 74AHCT257D - 40 °C to +125 °C SO16 74AHCT257PW - 40 °C to +125 °C TSSOP16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline...