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74AHC2G241DP - Dual buffer/line driver

Download the 74AHC2G241DP datasheet PDF. This datasheet also covers the 74AHC2G241 variant, as both devices belong to the same dual buffer/line driver family and are provided as variant models within a single manufacturer datasheet.

Description

The 74AHC2G241; 74AHCT2G241 is a high-speed Si-gate CMOS device.

The 74AHC2G241; 74AHCT2G241 is a dual non-inverting buffer/line driver with 3-state outputs.

The 3-state outputs are controlled by the output enable inputs 1OE and 2OE.

Features

  • Symmetrical output impedance.
  • High noise immunity.
  • ESD protection:.
  • HBM JESD22-A114E: exceeds 2000 V.
  • MM JESD22-A115-A: exceeds 200 V.
  • CDM JESD22-C101C: exceeds 1000 V.
  • Low power dissipation.
  • Balanced propagation delays.
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AHC2G241DP -40 °C to +125 °C 74AHC2G.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC2G241-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74AHC2G241 Dual buffer/line driver NXP Semiconductors
74AHC2G00 high-speed Si-gate CMOS device NXP
74AHC2G00-Q100 Dual 2-input NAND gate NXP
74AHC2G08 Dual 2-input AND gate NXP Semiconductors
74AHC2G126 Dual buffer/line driver NXP Semiconductors

Other Datasheets by Nexperia

Part Number Description
74AHC2G241DC Dual buffer/line driver
74AHC2G241 Dual buffer/line driver
74AHC2G241-Q100 Dual buffer/line driver
74AHC2G00 Dual 2-input NAND gate
74AHC2G00-Q100 Dual 2-input NAND gate

Full PDF Text Transcription

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74AHC2G241; 74AHCT2G241 Dual buffer/line driver; 3-state Rev. 4 — 16 January 2019 Product data sheet 1. General description The 74AHC2G241; 74AHCT2G241 is a high-speed Si-gate CMOS device. The 74AHC2G241; 74AHCT2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
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