74AHC373 latch equivalent, octal d-type transparant latch.
* Balanced propagation delays
* All inputs have a Schmitt-trigger action
* Common 3-state output enable input
* Inputs accepts voltages higher than VCC
A latch enable input (LE) and an output enable input (OE) are common to all latches.
When pin LE is HIGH, data at the D.
The 74AHC373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC373 consists of eight D-type transparent latches featuring separate D-type.
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