74AHC373 Description
The 74AHC373 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. The 74AHC373 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications.
74AHC373 Key Features
- Balanced propagation delays
- All inputs have a Schmitt-trigger action
- mon 3-state output enable input
- Inputs accepts voltages higher than VCC
- Functionally identical to the 74AHC573; 74AHCT573
- Input levels at CMOS input level
- ESD protection
- HBM EIA/JESD22-A114E exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- CDM EIA/JESD22-C101C exceeds 1000 V