74AHC373 Datasheet - nexperia

Octal D-type transparant latch

74AHC373 Features

* Balanced propagation delays

* All inputs have a Schmitt-trigger action

* Common 3-state output enable input

* Inputs accepts voltages higher than VCC

* Functionally identical to the 74AHC573; 74AHCT573

* Input levels at CMOS input level

* ESD

74AHC373 General Description

The 74AHC373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC373 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs fo.

74AHC373 Datasheet (227.45 KB)