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74AHC595-Q100 - 8-bit serial-in/serial-out or parallel-out shift register

Description

The 74AHC595-Q100; 74AHCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Wide supply voltage range from 2.0 V to 5.5 V.
  • Balanced propagation delays.
  • All inputs have Schmitt trigger action.
  • Overvoltage tolerant inputs to 5.5 V.
  • High noise immunity.
  • CMOS low power dissipation.
  • Input levels:.
  • The 74AHC595-Q100 operates with CMOS input levels.

📥 Download Datasheet

Datasheet Details

Part number 74AHC595-Q100
Manufacturer nexperia
File Size 288.72 KB
Description 8-bit serial-in/serial-out or parallel-out shift register
Datasheet download datasheet 74AHC595-Q100 Datasheet

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Full PDF Text Transcription

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74AHC595-Q100; 74AHCT595-Q100 8-bit serial-in/serial-out or parallel-out shift register with output latches Rev. 2 — 26 May 2020 Product data sheet 1. General description The 74AHC595-Q100; 74AHCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input.
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