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74AHCT138D Datasheet Preview

74AHCT138D Datasheet

3-to-8 line decoder/demultiplexer

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74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 5 — 10 September 2020
Product data sheet
1. General description
The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with
Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.
The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary
weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
outputs (Y0 to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every
output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to
32 lines) decoder with just four 74AHC138; 74AHCT138 devices and one inverter. The 74AHC138;
74AHCT138 can be used as an eight output demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be
permanently tied to their appropriate active HIGH or LOW state.
2. Features and benefits
Balanced propagation delays
All inputs have Schmitt-trigger action
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Inputs accepts voltages higher than VCC
For 74AHC138 only: operates with CMOS input levels
For 74AHCT138 only: operates with TTL input levels
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range
74AHC138D
-40 °C to +125 °C
74AHCT138D
74AHC138PW -40 °C to +125 °C
74AHCT138PW
74AHC138BQ -40 °C to +125 °C
74AHCT138BQ
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
Version
SOT109-1
SOT403-1
SOT763-1




nexperia

74AHCT138D Datasheet Preview

74AHCT138D Datasheet

3-to-8 line decoder/demultiplexer

No Preview Available !

Nexperia
4. Functional diagram
1
2
3
4 E1
5 E2
6 E3
Fig. 1. Logic symbol
A0
Y0 15
A1
Y1 14
A2
Y2
13
Y3 12
Y4
11
Y5 10
Y6
9
Y7
7
mna370
74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
DX 0 15
1
0
1 14
2
G
0
7
2
13
3
2
3 12
4 11
4
&
5 10
5
6
9
6
7
7
(a)
Fig. 2. IEC logic symbol
X/Y 0 15
1
1
1 14
2
2
3
4
2 13
3 12
4 11
4
&
5 10
5
6
9
6
EN
7
7
mna371
(b)
Fig. 3. Functional diagram
1 A0
2 A1
3 A2
3-to-8
DECODER
ENABLE
EXITING
4 E1
5 E2
6 E3
Y0 15
Y1 14
Y2 13
Y3 12
Y4 11
Y5 10
Y6 9
Y7 7
mna372
74AHC_AHCT138
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 September 2020
© Nexperia B.V. 2020. All rights reserved
2 / 15


Part Number 74AHCT138D
Description 3-to-8 line decoder/demultiplexer
Maker nexperia
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74AHCT138D Datasheet PDF






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