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74AHCT157-Q100 - Quad 2-input multiplexer

Download the 74AHCT157-Q100 datasheet PDF (74AHC157-Q100 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for quad 2-input multiplexer.

Description

The 74AHC/AHCT157-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no.

7A.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Balanced propagation delays.
  • All inputs have a Schmitt-trigger action.
  • Inputs accepts voltages higher than VCC.
  • Multiple input enable for easy expansion.
  • Ideal for memory chip select decoding.
  • For 74AHC157-Q100 only: operates with CMOS input levels.
  • For 74AHCT157-Q100 only: operates wi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC157-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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74AHC157-Q100; 74AHCT157-Q100 Quad 2-input multiplexer Rev. 2 — 10 September 2020 Product data sheet 1. General description The 74AHC/AHCT157-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT157-Q100 are quad 2-input multiplexer which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74AHC/AHCT157-Q100.
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