Download the 74AHCT164-Q100 datasheet PDF.
This datasheet also covers the 74AHC164-Q100 variant, as both devices belong to the same 8-bit serial-in/parallel-out shift register family and are provided as variant models within a single manufacturer datasheet.
General Description
The 74AHC164-Q100; 74AHCT164-Q100 is an 8-bit serial-in/parallel-out shift register.
Key Features
two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in.
Full PDF Text Transcription for 74AHCT164-Q100 (Reference)
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74AHCT164-Q100. For precise diagrams, and layout, please refer to the original PDF.
74AHC164-Q100; 74AHCT164-Q100 8-bit serial-in/parallel-out shift register Rev. 2 — 11 June 2020 Product data sheet 1. General description The 74AHC164-Q100; 74AHCT164-Q10...
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uct data sheet 1. General description The 74AHC164-Q100; 74AHCT164-Q100 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as tr
74AHCT164-Q100 Datasheet
