74ALVC162334ADGG Datasheet | Nexperia

74ALVC162334A 16-bit registered driver with inverted register enable and 30 Ω termination resistors (3-state) Rev. 03 - 13 December 2006 Product data sheet 1. General description The 74ALVC162334A is a 16-bit universal bus driver. Data flow is controlled by active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is stored in the latch/flip-flop. The 74ALVC162334A is designed with 30 Ω series resistors in both HIGH or LOW output stages. When OE is LOW, the outputs are active. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop. To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 2. Features I Wide supply voltage range of 1.2 V to 3.6 V I plies with JEDEC standard 8-1A I CMOS low power consumption I Direct interface with TTL levels I Current drive: ±24 m A at 3.0 V I MULTIBYTE flow-through standard pinout architecture I Low inductance multiple VCC and GND pins for minimum noise and ground bounce I Output drive capability 50 Ω transmission lines at 85 °C I Integrated 30 Ω termination resistors I Input diodes to acmodate strong drivers Nexperia 74ALVC162334A 16-bit registered driver (3-state) 3. Quick reference data Table 1. Quick reference data VCC = 3.3 V ± 0.3 V; GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 p F (see Figure 11). Symbol Parameter Conditions t PHL HIGH-to-LOW propagation delay An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 t PLH LOW-to-HIGH propagation delay An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 fmax maximum input clock frequency Figure 8 Ci input capacitance Cio...