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74ALVC162334ADGG - 16-bit registered driver

Download the 74ALVC162334ADGG datasheet PDF. This datasheet also covers the 74ALVC162334A variant, as both devices belong to the same 16-bit registered driver family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74ALVC162334A is a 16-bit universal bus driver.

Data flow is controlled by active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP).

When LE is LOW, the A to Y data flow is transparent.

Key Features

  • I Wide supply voltage range of 1.2 V to 3.6 V I Complies with JEDEC standard 8-1A I CMOS low power consumption I Direct interface with TTL levels I Current drive: ±24 mA at 3.0 V I.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74ALVC162334A-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74ALVC162334A 16-bit registered driver NXP
74ALVC162373 Low Voltage 16-Bit Transparent Latch Fairchild Semiconductor
74ALVC162374 Low Voltage 16-Bit D-Type Flip-Flop Fairchild Semiconductor
74ALVC162240 Low Voltage 16-Bit Inverting Buffer/Line Driver Fairchild Semiconductor
74ALVC162244 Low Voltage 16-Bit Buffer/Line Driver Fairchild Semiconductor

Other Datasheets by Nexperia

Part Number Description
74ALVC162334A 16-bit registered driver
74ALVC16244 16-bit buffer/line driver
74ALVC16245 16-bit transceiver
74ALVC162834A 18-bit registered driver
74ALVC162834ADGG 18-bit registered driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74ALVC162334A 16-bit registered driver with inverted register enable and 30 Ω termination resistors (3-state) Rev. 03 — 13 December 2006 Product data sheet 1. General description The 74ALVC162334A is a 16-bit universal bus driver. Data flow is controlled by active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is stored in the latch/flip-flop. The 74ALVC162334A is designed with 30 Ω series resistors in both HIGH or LOW output stages. When OE is LOW, the outputs are active. When OE is HIGH, the outputs go to the high-impedance OFF-state.