74ALVC573 Description
The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs enable (OE) input are mon to all latches. When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches.
74ALVC573 Key Features
- Wide supply voltage range from 1.65 V to 3.6 V
- 3.6 V tolerant inputs/outputs
- CMOS low power consumption
- Direct interface with TTL levels (2.7 V to 3.6 V)
- Power-down mode
- Latch-up performance exceeds 250 mA
- plies with JEDEC standards
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8B (2.7 V to 3.6 V)
74ALVC573 Applications
- Wide supply voltage range from 1.65 V to 3.6 V