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74ALVCH16501DGG Datasheet Preview

74ALVCH16501DGG Datasheet

18-bit universal bus transceiver

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74ALVCH16501
18-bit universal bus transceiver; 3-state
Rev. 6 — 13 March 2019
Product data sheet
1. General description
The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. Data flow in each direction is controlled by output enable
(OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For
A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB
is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the
A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is
HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output
enables are complimentary (OEAB is active HIGH, and OEBA is active LOW.
To ensure the high-impedance state during power-up or power-down, OEBA should be tied to
VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the
minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the
driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
Direct interface with TTL levels
Current drive ±24 mA at VCC = 3.0 V
Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in
transparent, latched or clocked mode
All inputs have bus hold circuitry
Output drive capability 50 Ω transmission lines at 85 °C
3-state non-inverting outputs for bus-oriented applications
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74ALVCH16501DGG -40 °C to +85 °C
Name
TSSOP56
Description
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
Version
SOT364-1




nexperia

74ALVCH16501DGG Datasheet Preview

74ALVCH16501DGG Datasheet

18-bit universal bus transceiver

No Preview Available !

Nexperia
4. Functional diagram
3 A0
5 A1
6 A2
8 A3
9 A4
10 A5
12 A6
13 A7
14 A8
15 A9
16 A10
17 A11
19 A12
20 A13
21 A14
23 A15
24 A16
26 A17
1 OEAB
2 LEAB
55 CPAB
Fig. 1. Logic symbol
B0 54
B1 52
B2 51
B3 49
B4 48
B5 47
B6 45
B7 44
B8 43
B9 42
B10 41
B11 40
B12 38
B13 37
B14 36
B15 34
B16 33
B17 31
OEBA 27
LEBA 28
CPBA 30
001aal718
74ALVCH16501
18-bit universal bus transceiver; 3-state
OEAB 1
CPAB 55
LEAB 2
OEBA 27
CPBA 30
LEBA 28
A0 3
A1 5
A2 6
A3 8
A4 9
A5 10
A6 12
A7 13
A8 14
A9 15
A10 16
A11 17
A12 19
A13 20
A14 21
A15 23
A16 24
A17 26
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D 1 1
4
1 6D
Fig. 2. IEC logic symbol
54 B0
52 B1
51 B2
49 B3
48 B4
47 B5
45 B6
44 B7
43 B8
42 B9
41 B10
40 B11
38 B12
37 B13
36 B14
34 B15
33 B16
31 B17
001aal717
VCC
Fig. 3. Bus hold circuit
data input
to internal circuit
001aal733
74ALVCH16501
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 13 March 2019
© Nexperia B.V. 2019. All rights reserved
2 / 15


Part Number 74ALVCH16501DGG
Description 18-bit universal bus transceiver
Maker nexperia
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