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74ALVCH16827DGG Datasheet Preview

74ALVCH16827DGG Datasheet

20-bit buffer/line driver

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74ALVCH16827
20-bit buffer/line driver, non-inverting; 3-state
Rev. 3 — 6 April 2018
Product data sheet
1 General description
The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with 3-state outputs for bus
oriented applications.
The 74ALVCH16827 consists of two 10-bit sections with separate output enable signals.
For either 10-bit buffer section, the two output enable (1OE0 and 1OE1 or 2OE0 and
2OE1) inputs must both be active. If either output enable input is high, the outputs of that
10-bit buffer section are in high impedance state.
The 74ALVCH16827 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2 Features and benefits
Wide supply voltage range of 1.2V to 3.6V
CMOS low power consumption
MultiByte flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels (2.7 V to 3.6 V)
Bus hold on data inputs
Output drive capability 50 Ω transmission lines at 85 °C
Current drive ±24 mA at 3.0 V
Complies with JEDEC standards:
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
CDM JESD22-C101E exceeds 1000 V
3 Ordering information
Table 1. Ordering information
Type number
Package
Temperature
range
Name
Description
74ALVCH16827DGG −40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
Version
SOT364-1




nexperia

74ALVCH16827DGG Datasheet Preview

74ALVCH16827DGG Datasheet

20-bit buffer/line driver

No Preview Available !

Nexperia
74ALVCH16827
20-bit buffer/line driver, non-inverting; 3-state
4 Functional diagram
55 54 52 51 49 48 47 45 44 43
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9
1 1OE0
56 1OE1
1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9
2 3 5 6 8 9 10 12 13 14
42 41 40 38 37 36 34 33 31 30
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9
28 2OE0
29 2OE1
2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2Y9
15 16 17 19 20 21 23 24 26 27
001aad 056
Figure 1. Logic symbol
nA0
nA1
nA2
nA3
nA4
1
56
& EN1
28
29
& EN2
55
54
11
2
3
52
5
51
6
49
8
48
9
47
10
45
12
44
13
43
14
42
41
12
15
16
40
17
38
19
37
20
36
21
34
23
33
24
31
26
30
27
001aad 055
Figure 2. IEC logic symbol
nA5
nA6
nA7
nA8
nA9
nOE0
nOE1
nY0
nY1
nY2
nY3
nY4
nY5
nY6
nY7
nY8
nY9
001aad 061
Figure 3. Logic diagram
VCC
Figure 4. Bus hold circuit
data input
to internal circuit
001aal733
74ALVCH16827
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 April 2018
© Nexperia B.V. 2018. All rights reserved.
2 / 13


Part Number 74ALVCH16827DGG
Description 20-bit buffer/line driver
Maker nexperia
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