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nexperia

74AUP1G373GS Datasheet Preview

74AUP1G373GS Datasheet

Low-power D-type transparent latch

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74AUP1G373
Low-power D-type transparent latch; 3-state
Rev. 7 — 27 March 2020
Product data sheet
1. General description
The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While the
latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW,
the latch stores the information that was present at the D-input one set-up time preceding the
HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the latch is available at
the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation
of input pin OE does not affect the state of the latch.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times
across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range
from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C




nexperia

74AUP1G373GS Datasheet Preview

74AUP1G373GS Datasheet

Low-power D-type transparent latch

No Preview Available !

Nexperia
74AUP1G373
Low-power D-type transparent latch; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP1G373GW -40 °C to +125 °C SC-88
74AUP1G373GM -40 °C to +125 °C XSON6
74AUP1G373GF -40 °C to +125 °C XSON6
74AUP1G373GN -40 °C to +125 °C XSON6
74AUP1G373GS -40 °C to +125 °C XSON6
Description
Version
plastic surface-mounted package; 6 leads
SOT363
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 × 1.0 × 0.35 mm
SOT1115
extremely thin small outline package; no leads;
6 terminals; body 1.0 × 1.0 × 0.35 mm
SOT1202
4. Marking
Table 2. Marking
Type number
74AUP1G373GW
74AUP1G373GM
74AUP1G373GF
74AUP1G373GN
74AUP1G373GS
Marking code [1]
aW
aW
aW
aW
aW
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
D
DQ
Q
3D Q4
1 LE
OE
6
001aae247
Fig. 1. Logic symbol
1
C1
3
4
6
EN
001aae248
Fig. 2. IEC logic symbol
LE LE
LE
OE
001aae249
Fig. 3. Logic diagram
74AUP1G373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 27 March 2020
© Nexperia B.V. 2020. All rights reserved
2 / 22


Part Number 74AUP1G373GS
Description Low-power D-type transparent latch
Maker nexperia
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74AUP1G373GS Datasheet PDF






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