Low-power configurable gate with voltage-level translator
Rev. 6 — 28 March 2017
Product data sheet
1 General description
The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected
to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 2.3 V to 3.6 V.
The 74AUP1T97 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire VCC range.
2 Features and benefits
• Wide supply voltage range from 2.3 V to 3.6 V
• High noise immunity
• ESD protection:
– HBM JESD22-A114F Class 3A exceeds 5 000 V
– MM JESD22-A115-A exceeds 200 V
– CDM JESD22-C101E exceeds 1 000 V
• Low static power consumption; ICC = 1.5 μA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of VCC
• IOFF circuitry provides partial power-down mode operation
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C