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74AUP1T98 Datasheet Low-power Configurable Gate

Manufacturer: Nexperia

Overview: 74AUP1T98 Low-power configurable gate with voltage-level translator Rev. 7 — 27 January 2022 Product data sheet 1.

General Description

The 74AUP1T98 is a configurable multiple function gate with level translating, Schmitt-trigger inputs.

The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer;

using the 3-bit input.

Key Features

  • Wide supply voltage range from 2.3 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Complies with JEDEC standards.
  • JESD8-12 (0.8 V to 1.3 V).
  • JESD8-11 (0.9 V to 1.65 V).
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8C (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F Class 3A exceeds 5000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101E exceeds 1000.

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More Datasheets from Nexperia

Part Number Description
74AUP1T98-Q100 Low-power configurable gate
74AUP1T97 Low-power configurable gate
74AUP1T00 Low-power 2-input NAND gate
74AUP1T02 Low-power 2-input NOR gate
74AUP1T04 Low-power inverter
74AUP1T08 Low-power 2-input AND gate
74AUP1T14 Low-power inverter
74AUP1T17 Low-power buffer
74AUP1T32 Low-power 2-input OR-gate
74AUP1T34 Low-power dual supply translating buffer