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74HC109DB Datasheet Preview

74HC109DB Datasheet

Dual JK flip-flop

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74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
Rev. 4 — 1 April 2020
Product data sheet
1. General description
The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual nJ and
nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and
nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently
of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described
in the mode select function table. The nJ and nK inputs must be stable one set-up time prior
to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation
as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes.
It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall
times.
2. Features and benefits
Input levels:
For 74HC109: CMOS level
For 74HCT109: TTL level
J and K inputs for easy D-type flip-flop
Toggle flip-flop or "do nothing" mode
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range
74HC109D
-40 °C to +125 °C
74HCT109D
74HC109DB
-40 °C to +125 °C
74HCT109DB
74HCT109PW -40 °C to +125 °C
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1




nexperia

74HC109DB Datasheet Preview

74HC109DB Datasheet

Dual JK flip-flop

No Preview Available !

Nexperia
4. Functional diagram
5 11
1SD 2SD
SD
2
14
1J
2J
J
Q
1Q
2Q
6
10
4
12
3
13
1CP
2CP
1K
2K
CP
FF
K
Q
RD
1Q
2Q
7
9
1RD 2RD
1 15
mna858
Fig. 1. Logic symbol
C
K
J
C
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
5S
2 1J
4
C1
3 1K
1R
11 S
6
14
1J
10
12
C1
7
13
1K
9
15 R
(a)
Fig. 2. IEC logic symbol
(b)
mna856
Q
C
C
C
Q
C
C
C
S
R
CP
C
C
Fig. 3. Logic diagram (one flip-flop)
aaa-024066
74HC_HCT109
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 1 April 2020
© Nexperia B.V. 2020. All rights reserved
2 / 17


Part Number 74HC109DB
Description Dual JK flip-flop
Maker nexperia
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74HC109DB Datasheet PDF






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