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74HC163-Q100 Datasheet Preview

74HC163-Q100 Datasheet

Presettable synchronous 4-bit binary counter

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74HC163-Q100; 74HCT163-Q100
Presettable synchronous 4-bit binary counter; synchronous
reset
Rev. 2 — 12 October 2018
Product data sheet
1. General description
The 74HC163-Q100; 74HCT163-Q100 is a synchronous presettable binary counter with an internal
look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously
on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset
to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes
the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of
the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A
LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition
on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and
CEP. This synchronous reset feature enables the designer to modify the maximum count with
only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters.
Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal
count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded
stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of VCC.
The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock
frequency for the cascaded counters according to the following formula:
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Complies with JEDEC standard no. 7A
Input levels:
For 74HC163: CMOS level
For 74HCT163: TTL level
Synchronous counting and loading
2 count enable inputs for n-bit cascading
Synchronous reset
Positive-edge triggered clock
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)
Multiple package options




nexperia

74HC163-Q100 Datasheet Preview

74HC163-Q100 Datasheet

Presettable synchronous 4-bit binary counter

No Preview Available !

Nexperia
74HC163-Q100; 74HCT163-Q100
Presettable synchronous 4-bit binary counter; synchronous reset
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC163D-Q100
-40 °C to +125 °C
74HCT163D-Q100
74HC163PW-Q100
-40 °C to +125 °C
74HCT163PW-Q100
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
TSSOP16 plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT403-1
4. Functional diagram
93456
PE D0 D1 D2 D3
7 CEP
10 CET
2 CP
TC 15
1 MR
Q0 Q1 Q2 Q3
14 13 12 11
aaa-012184
Fig. 1. Logic symbol
9 PE
1 MR
3456
D0 D1 D2 D3
PARALLEL
LOAD CIRCUITRY
10 CET
7 CEP
2 CP
D
INH
CP
BINARY
COUNTER
Q0 Q1 Q2 Q3
14 13 12 11
Fig. 2. Functional diagram
Fig. 3. IEC logic symbol
1
CTR4
2R
9 M1
7 G3
10 G4
2 C2/1,3,4+
3 1,2D
4
5
6
14
13
12
11
4CT = 15 15
aaa-012185
TC 15
aaa-012186
74HC_HCT163_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 12 October 2018
© Nexperia B.V. 2018. All rights reserved
2 / 19


Part Number 74HC163-Q100
Description Presettable synchronous 4-bit binary counter
Maker nexperia
Total Page 19 Pages
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