74HC40103 Description
The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP).
74HC40103 Key Features
- Cascadable
- Synchronous or asynchronous preset
- Low-power dissipation
- plies with JEDEC standard no. 7A
- CMOS input levels
- ESD protection
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- Multiple package options
- Specified from 40 C to +80 C and from 40 C to +125 C