74HC4520PW Datasheet PDF - nexperia Dual 4-bit synchronous binary counter Specs

74HC4520PW - Dual 4-bit synchronous binary counter

This page provides the datasheet information for the 74HC4520PW, a member of the 74HC4520 Dual 4-bit synchronous binary counter family.

Datasheet Summary

Description

The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1).

They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR).

Features

Wide supply voltage range from 2.0 V to 6.0 V.
CMOS low power dissipation.
High noise immunity.
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
Complies with JEDEC standards:.
JESD8C (2.7 V to 3.6 V).
JESD7A (2.0 V to 6.0 V).
Input levels:.
For 74HC4520: CMOS level.
For 74HCT4520: TTL level.
ESD protection:.
HBM JESD22-A114F exceeds 2000 V.
MM JESD22-A115-A exce.

Datasheet Details

Part number	74HC4520PW
Manufacturer	nexperia
File Size	249.03 KB
Description	Dual 4-bit synchronous binary counter
Datasheet	74HC4520PW Datasheet
Additional preview pages of the 74HC4520PW datasheet.

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Full PDF Text Transcription

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74HC4520; 74HCT4520 Dual 4-bit synchronous binary counter Rev. 6 — 9 October 2020 Product data sheet 1. General description The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 when nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR, resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes.

Published: Dec 27, 2020 |