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74HC75D - Quad bistable transparant latch

Download the 74HC75D datasheet PDF. This datasheet also covers the 74HC75 variant, as both devices belong to the same quad bistable transparant latch family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC75 is a quad bistable transparent latch with complementary outputs.

Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34).

When LEnn is HIGH, the data enters the latches and appears at the nQ outputs.

Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Complementary Q and Q outputs.
  • VCC and GND on the center pins.
  • CMOS input levels.
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC75-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC75D
Manufacturer Nexperia
File Size 257.30 KB
Description Quad bistable transparant latch
Datasheet download datasheet 74HC75D Datasheet

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Other Datasheets by Nexperia

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74HC75 Quad bistable transparant latch
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC75 Quad bistable transparent latch Rev. 6 — 17 January 2024 Product data sheet 1. General description The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.
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