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74HCT107D Datasheet Dual JK flip-flop

Manufacturer: Nexperia

Download the 74HCT107D datasheet PDF. This datasheet also includes the 74HC107 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (74HC107-nexperia.pdf) that lists specifications for multiple related part numbers.

General Description

The 74HC107;

74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs.

The reset is an asynchronous active LOW input and operates independently of the clock input.

Overview

74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev.

7 — 20 February 2024 Product data sheet 1.

Key Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Input levels:.
  • The 74HC107: CMOS levels.
  • The 74HCT107: TTL levels.
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
  • CD.

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