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74HCT112PW Datasheet Preview

74HCT112PW Datasheet

Dual JK flip-flop

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74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 3 — 9 August 2016
Product data sheet
1. General description
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features
individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has
complementary nQ and nQ outputs. The set and reset are asynchronous active LOW
inputs and operate independently of the clock input. The J and K inputs control the state
changes of the flip-flops as described in the mode select function table. The J and K
inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for
predictable operation. Inputs include clamp diodes that enable the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features and benefits
Input levels:
For 74HC112: CMOS level
For 74HCT112: TTL level
Asynchronous set and reset
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
Version
74HC112D
40 C to +125 C SO16
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT112D
74HC112DB 40 C to +125 C
74HCT112DB
SSOP16 plastic shrink small outline package; 16 leads; body width SOT338-1
5.3 mm
74HC112PW 40 C to +125 C
74HCT112PW
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1




nexperia

74HCT112PW Datasheet Preview

74HCT112PW Datasheet

Dual JK flip-flop

No Preview Available !

Nexperia
4. Functional diagram
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
 
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Fig 1. Logic symbol

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Fig 2. IEC logic symbol
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Fig 3. Logic diagram (one flip-flop)
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74HC_HCT112
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 August 2016
© Nexperia B.V. 2017. All rights reserved
2 of 20


Part Number 74HCT112PW
Description Dual JK flip-flop
Maker nexperia
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