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74HCT259 - 8-bit addressable latch

Download the 74HCT259 datasheet PDF. This datasheet also covers the 74HC259 variant, as both devices belong to the same 8-bit addressable latch family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC259; 74HCT259 is an 8-bit addressable latch.

Key Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Combined demultiplexer and 8-bit latch.
  • Serial-to-parallel capability.
  • Output from each storage bit available.
  • Random (addressable) data entry.
  • Easily expandable.
  • Common reset input.
  • Useful as a 3.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC259-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT259
Manufacturer Nexperia
File Size 312.13 KB
Description 8-bit addressable latch
Datasheet download datasheet 74HCT259 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74HCT251 8-input multiplexer Philips
74HCT253 Dual 4-input multiplexer Philips
74HCT257 Quad 2-input multiplexer Philips
74HCT257 High-Speed CMOS Logic Quad 2-Input Multiplexer Texas Instruments
74HCT258 Quad 2-input multiplexer Philips

Other Datasheets by Nexperia

Part Number Description
74HCT259-Q100 8-bit addressable latch
74HCT259D 8-bit addressable latch
74HCT251 8-input multiplexer
74HCT251-Q100 8-input multiplexer
74HCT251D 8-input multiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC259; 74HCT259 8-bit addressable latch Rev. 8 — 5 December 2022 Product data sheet 1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states. In memory mode, all latches retain their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes.