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74HCT259PW Datasheet Preview

74HCT259PW Datasheet

8-bit addressable latch

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74HC259; 74HCT259
8-bit addressable latch
Rev. 7 — 2 September 2020
Product data sheet
1. General description
The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of
operation. In the addressable latch mode, data on the D input is written into the latch addressed
by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches
will retain their previous states. In memory mode, all latches retain their previous states and are
unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the
addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs
are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
Combined demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Input levels:
For 74HC259: CMOS level
For 74HCT259: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22E exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C




nexperia

74HCT259PW Datasheet Preview

74HCT259PW Datasheet

8-bit addressable latch

No Preview Available !

Nexperia
74HC259; 74HCT259
8-bit addressable latch
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74HC259D
-40 °C to +125 °C SO16
74HCT259D
74HC259PW -40 °C to +125 °C TSSOP16
74HCT259PW
74HC259BQ
-40 °C to +125 °C DHVQFN16
74HCT259BQ
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
Version
SOT109-1
SOT403-1
SOT763-1
4. Functional diagram
14
LE
Q0 4
13 D
Q1 5
Q2 6
Q3 7
1 A0
Q4 9
2 A1
Q5 10
3 A2
Q6 11
12
Q7
MR
15 mna573
Fig. 1. Logic symbol
13 Z9
15 G8
14
G10
1
DX
9,10D
0
1
C10
8R
4
0
2
3
G
0
7
2
1
5
6
2
7
3
9
4
10
5
11
6
12
7
mna572
Fig. 2. IEC logic symbol
Fig. 3. Functional diagram
1 A0
2 A1
3 A2
1-of-8
DECODER
14 LE
15 MR
13 D
Q0 4
Q1 5
Q2 6
Q3 7
8 LATCHES Q4 9
Q5 10
Q6 11
Q7 12
mna571
74HC_HCT259
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 2 September 2020
© Nexperia B.V. 2020. All rights reserved
2 / 17


Part Number 74HCT259PW
Description 8-bit addressable latch
Maker nexperia
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74HCT259PW Datasheet PDF






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