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74HCT373-Q100 - Octal D-type transparent latch

Download the 74HCT373-Q100 datasheet PDF (74HC373-Q100 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for octal d-type transparent latch.

Description

The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch with 3-state outputs.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Input levels:.
  • For 74HC3.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC373-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Rev. 2 — 22 July 2020 Product data sheet 1. General description The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes.
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