74HCT4520D Datasheet | Nexperia

description The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (n CP0 and n CP1). They have buffered outputs from all 4 bit positions (n Q0 to n Q3) and an asynchronous master reset input (n MR). The counter advances on the LOW-to-HIGH transition of n CP0 when n CP1 is HIGH. It also advances on the HIGH-to-LOW transition of n CP1 when n CP0 is LOW. Either n CP0 or n CP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on n MR, resets the counter (n Q0 to n Q3 = LOW) independent of n CP0 and n CP1. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits - Wide supply voltage range from 2.0 V to 6.0 V - CMOS low power dissipation - High noise immunity - Latch-up performance exceeds 100 m A per JESD 78 Class II Level B - plies with JEDEC standards: - JESD8C (2.7 V to 3.6 V) - JESD7A (2.0 V to 6.0 V) - Input levels: - For 74HC4520: CMOS level - For 74HCT4520: TTL level - ESD protection: - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V - Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Applications - Multistage synchronous counting - Multistage asynchronous counting - Frequency dividers 4. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC4520D -40 °C to +125 °C 74HC4520PW -40 °C to +125 °C Name SO16 TSSOP16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT403-1 Nexperia 74HC4520; 74HCT4520 Dual 4-bit synchronous binary counter 5. Functional diagram Fig. 1. Functional...