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74HCT4520D - Dual 4-bit synchronous binary counter

Download the 74HCT4520D datasheet PDF. This datasheet also covers the 74HC4520 variant, as both devices belong to the same dual 4-bit synchronous binary counter family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1).

They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR).

Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Input levels:.
  • For 74HC4520: CMOS level.
  • For 74HCT4520: TTL level.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exce.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC4520-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT4520D
Manufacturer Nexperia
File Size 249.03 KB
Description Dual 4-bit synchronous binary counter
Datasheet download datasheet 74HCT4520D Datasheet

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Other Datasheets by Nexperia

Part Number Description
74HCT4520 Dual 4-bit synchronous binary counter
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC4520; 74HCT4520 Dual 4-bit synchronous binary counter Rev. 6 — 9 October 2020 Product data sheet 1. General description The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 when nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR, resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes.
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