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74HCT595 - serial or parallel-out shift register

Download the 74HCT595 datasheet PDF (74HC595 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for serial or parallel-out shift register.

Description

The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • 8-bit serial input.
  • 8-bit serial or parallel output.
  • Storage register with 3-state outputs.
  • Shift register with direct clear.
  • 100 MHz (typical) shift out frequency.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC595-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT595
Manufacturer nexperia
File Size 323.46 KB
Description serial or parallel-out shift register
Datasheet download datasheet 74HCT595 Datasheet

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Full PDF Text Transcription

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74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 12 — 20 March 2024 Product data sheet 1. General description The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input.
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