74LV132
Quad 2-input NAND Schmitt trigger
Rev. 7 — 20 May 2020
Product data sheet
1. General description
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC132 and 74HCT132.
The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are
capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis
voltage VH.
2. Features and benefits
• Wide operating voltage: 1.0 V to 5.5 V
• Optimized for low voltage applications: 1.0 V to 3.6 V
• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
• Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
• Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Applications
• Wave and pulse shapers for highly noisy environments
• Astable multivibrators
• Monostable multivibrators
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
74LV132D
-40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LV132DB
-40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads; body
width 5.3 mm
74LV132PW
-40 °C to +125 °C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74LV132BQ
-40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
