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74LV132PW Datasheet Preview

74LV132PW Datasheet

Quad 2-input NAND Schmitt trigger

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74LV132
Quad 2-input NAND Schmitt trigger
Rev. 7 — 20 May 2020
Product data sheet
1. General description
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC132 and 74HCT132.
The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are
capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis
voltage VH.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Applications
Wave and pulse shapers for highly noisy environments
Astable multivibrators
Monostable multivibrators
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
74LV132D
-40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LV132DB
-40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads; body
width 5.3 mm
74LV132PW
-40 °C to +125 °C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74LV132BQ
-40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1




nexperia

74LV132PW Datasheet Preview

74LV132PW Datasheet

Quad 2-input NAND Schmitt trigger

No Preview Available !

Nexperia
5. Functional diagram
1 1A
2 1B
1Y 3
4 2A
5 2B
2Y 6
9 3A
10 3B
3Y 8
12 4A
13 4B
Fig. 1. Logic symbol
4Y 11
mna407
1
&
3
2
4
&
6
5
9
&
8
10
12
&
11
13
mna408
Fig. 2. IEC logic symbol
6. Pinning information
74LV132
Quad 2-input NAND Schmitt trigger
A
Y
B
mna409
Fig. 3. Logic diagram (one gate)
6.1. Pinning
74LV132
1A 1
1B 2
14 VCC
13 4B
1Y 3
12 4A
2A 4
11 4Y
2B 5
10 3B
2Y 6
9 3A
GND 7
8 3Y
001aac203
Fig. 4. Pin configuration SOT108-1 (SO14),
SOT337-1 (SSOP14) and SOT402-1 (TSSOP14)
74LV132
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
VCC(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aah099
Fig. 5.
Transparent top view
(1) This is not a supply pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to VCC
Pin configuration SOT762-1 (DHVQFN14)
74LV132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 20 May 2020
© Nexperia B.V. 2020. All rights reserved
2 / 15


Part Number 74LV132PW
Description Quad 2-input NAND Schmitt trigger
Maker nexperia
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74LV132PW Datasheet PDF






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