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74LV164PW Datasheet Preview

74LV164PW Datasheet

8-bit serial-in/parallel-out shift register

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74LV164
8-bit serial-in/parallel-out shift register
Rev. 5 — 23 September 2020
Product data sheet
1. General description
The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each
of the eight stages. Data is entered serially through one of two inputs (DSA or DSB) and either
input can be used as an active HIGH enable for data entry through the other input. Both inputs
must be connected together or an unused input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and
enters into Q0, which is the logical AND-function of the two data inputs (DSA and DSB) that existed
one set-up time prior to the rising clock edge.
A LOW on the master reset input (MR) overrides all other inputs and clears the register
asynchronously, forcing all outputs LOW.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low-voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce): < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
Typical VOHV (output VOH undershoot): > 2 V at VCC = 3.3 V and Tamb = 25 °C
Gated serial data inputs
Asynchronous master reset
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +80 °C and from -40 °C to +125 °C.
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74LV164D -40 °C to +125 °C SO14
74LV164DB -40 °C to +125 °C SSOP14
74LV164PW -40 °C to +125 °C TSSOP14
74LV164BQ -40 °C to +125 °C DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1




nexperia

74LV164PW Datasheet Preview

74LV164PW Datasheet

8-bit serial-in/parallel-out shift register

No Preview Available !

Nexperia
4. Functional diagram
DSA 1
DSB 2
CP
MR
Fig. 1. Logic symbol
3 Q0
4 Q1
5 Q2
6 Q3
10 Q4
8
11 Q5
12 Q6
9
13 Q7
001aac423
DSA 1
DSB 2
CP 8
MR 9
Fig. 3. Functional diagram
5. Pinning information
74LV164
8-bit serial-in/parallel-out shift register
SRG8
8
C1/
9R
1
2
&
1D
3
4
5
6
10
11
12
13
001aac424
Fig. 2. IEC logic symbol
8-BIT SERIAL- IN/PARALLEL- OUT
SHIFT REGISTER
3 4 5 6 10 11 12 13
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
001aac425
5.1. Pinning
74LV164
DSA 1
DSB 2
Q0 3
Q1 4
Q2 5
Q3 6
GND 7
14 VCC
13 Q7
12 Q6
11 Q5
10 Q4
9 MR
8 CP
001aac422
Fig. 4. Pin configuration SOT108-1 (SO14), SOT337-1
(SSOP14) and SOT402-1 (TSSOP14)
74LV164
terminal 1
index area
DSB 2
Q0 3
Q1 4
Q2 5
Q3 6
VCC(1)
13 Q7
12 Q6
11 Q5
10 Q4
9 MR
001aac429
Fig. 5.
Transparent top view
(1) This is not a supply pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to VCC.
Pin configuration SOT762-1 (DHVQFN14)
74LV164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 23 September 2020
© Nexperia B.V. 2020. All rights reserved
2 / 16


Part Number 74LV164PW
Description 8-bit serial-in/parallel-out shift register
Maker nexperia
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