900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






nexperia

74LVC00AD Datasheet Preview

74LVC00AD Datasheet

Quad 2-input NAND gate

No Preview Available !

74LVC00A
Quad 2-input NAND gate
Rev. 8 — 24 August 2020
Product data sheet
1. General description
The 74LVC00A provides four 2-input NAND gates.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC00AD -40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LVC00ADB -40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
74LVC00APW -40 °C to +125 °C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74LVC00ABQ -40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1




nexperia

74LVC00AD Datasheet Preview

74LVC00AD Datasheet

Quad 2-input NAND gate

No Preview Available !

Nexperia
4. Functional diagram
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
mna212
Fig. 1. Logic symbol
1
2
&
3
4
5
&
6
9
10
&
8
12
13
&
11
mna246
Fig. 2. IEC logic symbol
5. Pinning information
74LVC00A
Quad 2-input NAND gate
A
Y
B
mna211
Fig. 3. Logic diagram (one gate)
5.1. Pinning
74LVC00A
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
001aac938
Fig. 4. Pin configuration for SOT108-1 (SO14),
SOT337-1 (SSOP14) and SOT402-1 (TSSOP14)
74LVC00A
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND (1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aac939
Transparent top view
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5. Pin configuration for SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8,11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
74LVC00A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 24 August 2020
© Nexperia B.V. 2020. All rights reserved
2 / 13


Part Number 74LVC00AD
Description Quad 2-input NAND gate
Maker nexperia
PDF Download

74LVC00AD Datasheet PDF






Similar Datasheet

1 74LVC00A LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE
STMicroelectronics
2 74LVC00A QUADRUPLE 2-INPUT NAND GATES
Diodes
3 74LVC00A Low-Voltage CMOS Quad 2-Input NAND Gate
ON Semiconductor
4 74LVC00A Quad 2-input NAND gate
nexperia
5 74LVC00A-Q100 Quad 2-input NAND gate
nexperia
6 74LVC00ABQ Quad 2-input NAND gate
nexperia
7 74LVC00AD Quad 2-input NAND gate
nexperia
8 74LVC00ADB Quad 2-input NAND gate
nexperia
9 74LVC00AMTR LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE
STMicroelectronics





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy