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74LVC02ABQ Datasheet Preview

74LVC02ABQ Datasheet

Quad 2-input NOR gate

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74LVC02A
Quad 2-input NOR gate
Rev. 9 — 24 August 2020
Product data sheet
1. General description
The 74LVC02A provides four 2-input NOR gates.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
74LVC02AD
-40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LVC02ADB
-40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
74LVC02APW
-40 °C to +125 °C
TSSOP14 plastic thin shrink small outline package;
14 leads; body width 4.4 mm
74LVC02ABQ
-40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1




nexperia

74LVC02ABQ Datasheet Preview

74LVC02ABQ Datasheet

Quad 2-input NOR gate

No Preview Available !

Nexperia
4. Functional diagram
2
1
1
3
2 1A
3 1B
5 2A
6 2B
8 3A
9 3B
11 4A
12 4B
1Y 1
2Y 4
3Y 10
4Y 13
mna216
Fig. 1. Logic symbol
5
1
4
6
8
1
10
9
11
1
13
12
mna217
Fig. 2. IEC logic symbol
5. Pinning information
74LVC02A
Quad 2-input NOR gate
A
Y
B
mna215
Fig. 3. Logic diagram (one gate)
5.1. Pinning
74LVC02A
1Y 1
1A 2
1B 3
2Y 4
2A 5
2B 6
GND 7
14 VCC
13 4Y
12 4B
11 4A
10 3Y
9 3B
8 3A
001aac919
Fig. 4. Pin configuration for SOT108-1 (SO14),
SOT337-1 (SSOP14) and SOT402-1 (TSSOP14)
74LVC02A
terminal 1
index area
1A 2
1B 3
2Y 4
2A 5
2B 6
GND(1)
13 4Y
12 4B
11 4A
10 3Y
9 3B
001aac920
Fig. 5.
Transparent top view
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Pin configuration for SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1Y to 4Y
1A to 4A
1B to 4B
GND
VCC
Pin
1, 4, 10, 13
2, 5, 8, 11
3, 6, 9,12
7
14
Description
data output
data input
data input
ground (0 V)
supply voltage
74LVC02A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 24 August 2020
© Nexperia B.V. 2020. All rights reserved
2 / 13


Part Number 74LVC02ABQ
Description Quad 2-input NOR gate
Maker nexperia
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