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74LVC10AD Datasheet Preview

74LVC10AD Datasheet

Triple 3-input NAND gate

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74LVC10A
Triple 3-input NAND gate
Rev. 5 — 17 November 2011
Product data sheet
1. General description
The 74LVC10A provides three 3-input NAND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC10AD 40 C to +125 C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LVC10ADB 40 C to +125 C SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
74LVC10APW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74LVC10ABQ 40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1




nexperia

74LVC10AD Datasheet Preview

74LVC10AD Datasheet

Triple 3-input NAND gate

No Preview Available !

Nexperia
4. Functional diagram
74LVC10A
Triple 3-input NAND gate
1 1A
2 1B
13 1C
3 2A
4 2B
5 2C
9 3A
10 3B
11 3C
1Y 12
2Y 6
3Y 8
mna757
Fig 1. Logic symbol
1
2
&
12
13
3
4
&
6
5
9
10
&
8
11
mna759
Fig 2. IEC logic symbol
5. Pinning information
A
B
Y
C
mna758
Fig 3. Logic diagram for one gate
5.1 Pinning
74LVC10A
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
14 VCC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
001aad047
Fig 4. Pin configuration for SO14 and (T)SSOP14
74LVC10A
terminal 1
index area
1B 2
2A 3
2B 4
2C 5
2Y 6
GND(1)
13 1C
12 1Y
11 3C
10 3B
9 3A
001aad048
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration for DHVQFN14
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1A, 2A, 3A
1, 3, 9
1B, 2B, 3B
2, 4, 10
1C, 2C, 3C
13, 5, 11
Description
data input
data input
data input
74LVC10A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 17 November 2011
© Nexperia B.V. 2017. All rights reserved
2 of 14


Part Number 74LVC10AD
Description Triple 3-input NAND gate
Maker nexperia
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74LVC10AD Datasheet PDF






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