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74LVC125ADB Datasheet Preview

74LVC125ADB Datasheet

Quad buffer/line driver

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74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Rev. 8 — 5 May 2020
Product data sheet
1. General description
The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs (nY) that
are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a
high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to
the outputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC125AD -40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LVC125ADB -40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
74LVC125APW -40 °C to +125 °C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74LVC125ABQ -40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1




nexperia

74LVC125ADB Datasheet Preview

74LVC125ADB Datasheet

Quad buffer/line driver

No Preview Available !

Nexperia
4. Functional diagram
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
2 1A
1Y 3
1 1OE
5 2A
2Y 6
4 2OE
9 3A
3Y 8
10 3OE
12 4A
4Y 11
13 4OE
mna228
Fig. 1. Logic symbol
2
1
3
1
EN1
5
6
4
9
8
10
12
11
13
mna229
Fig. 2. IEC logic symbol
5. Pinning information
nA
nOE
Fig. 3. Logic diagram
nY
mna227
5.1. Pinning
1OE 1
14 VCC
1A 2
13 4OE
1Y 3
12 4A
2OE 4
125
11 4Y
2A 5
10 3OE
2Y 6
9 3A
GND 7
8 3Y
001aad045
Fig. 4. Pin configuration for SOT108-1 (SO14),
SOT337-1 (SSOP14) and SOT402-1 (TSSOP14)
terminal 1
index area
1A 2
1Y 3
2OE 4
2A 5
2Y 6
125
GND(1)
13 4OE
12 4A
11 4Y
10 3OE
9 3A
001aad046
Fig. 5.
Transparent top view
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Pin configuration for SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1OE, 2OE, 3OE, 4OE
1A, 2A, 3A, 4A
1Y, 2Y, 3Y, 4Y
GND
VCC
Pin
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
Description
data enable input (active LOW)
data input
data output
ground (0 V)
supply voltage
74LVC125A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 5 May 2020
© Nexperia B.V. 2020. All rights reserved
2 / 14


Part Number 74LVC125ADB
Description Quad buffer/line driver
Maker nexperia
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