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74LVC132APW Datasheet Preview

74LVC132APW Datasheet

Quad 2-input NAND Schmitt trigger

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74LVC132A
Quad 2-input NAND Schmitt trigger
Rev. 4 — 6 July 2020
Product data sheet
1. General description
The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of
transforming slowly-changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference between
the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V environment.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
5 V tolerant inputs for interfacing with 5 V logic
CMOS low-power consumption
Direct interface with TTL levels
Unlimited input rise and fall times
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Applications
Wave and pulse shapers for highly noisy environments
Astable multivibrator
Monostable multivibrator.
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC132AD
-40 °C to +125 °C SO14
74LVC132APW -40 °C to +125 °C TSSOP14
74LVC132ABQ -40 °C to +125 °C DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1




nexperia

74LVC132APW Datasheet Preview

74LVC132APW Datasheet

Quad 2-input NAND Schmitt trigger

No Preview Available !

Nexperia
5. Functional diagram
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
mna212
Fig. 1. Logic symbol
1
2
&
3
4
5
&
6
9
10
&
8
12
13
&
11
mna246
Fig. 2. IEC logic symbol
6. Pinning information
74LVC132A
Quad 2-input NAND Schmitt trigger
A
Y
B
001aac532
Fig. 3. Logic diagram (one gate)
6.1. Pinning
74LVC132A
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
001aaf590
Fig. 4. Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
6.2. Pin description
Table 2. Pin description
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
VCC
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
74LVC132A
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aaf591
Transparent top view
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5. Pin configuration SOT762-1 (DHVQFN14)
Description
data input
data input
data output
ground (0 V)
supply voltage
74LVC132A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 July 2020
© Nexperia B.V. 2020. All rights reserved
2 / 14


Part Number 74LVC132APW
Description Quad 2-input NAND Schmitt trigger
Maker nexperia
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