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74LVC161 - Presettable synchronous 4-bit binary counter

Description

The 74LVC161 is a synchronous presettable binary counter with an internal look-head carry.

Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP).

The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW.

Features

  • Overvoltage tolerant inputs to 5.5 V.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power dissipation.
  • Direct interface with TTL levels.
  • Asynchronous reset.
  • Synchronous counting and loading.
  • Two count enable inputs for n-bit cascading.
  • Positive edge-triggered clock.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.

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Datasheet Details

Part number 74LVC161
Manufacturer nexperia
File Size 293.44 KB
Description Presettable synchronous 4-bit binary counter
Datasheet download datasheet 74LVC161 Datasheet

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Full PDF Text Transcription

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74LVC161 Presettable synchronous 4-bit binary counter; asynchronous reset Rev. 7 — 22 September 2021 Product data sheet 1. General description The 74LVC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET).
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