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74LVC161PW Datasheet Preview

74LVC161PW Datasheet

Presettable synchronous 4-bit binary counter

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74LVC161
Presettable synchronous 4-bit binary counter; asynchronous
reset
Rev. 6 — 30 September 2013
Product data sheet
1. General description
The 74LVC161 is a synchronous presettable binary counter which features an internal
look-ahead carry and can be used for high-speed counting. Synchronous operation is
provided by having all flip-flops clocked simultaneously on the positive-going edge of the
clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level
or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting
action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter
on the positive-going edge of the clock (provided that the set-up and hold time
requirements for PE are met). Preset takes place regardless of the levels at count enable
inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four
outputs of the flip-flops (pins Q0 to Q3) to LOW-level regardless of the levels at input pins
CP, PE, CET and CEP (thus providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs
(pin CEP and CET) must be HIGH to count. The CET input is fed forward to enable the
terminal count output (pin TC). The TC output thus enabled will produce a HIGH output
pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be
used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by tPHL
(propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula:
fmax
=
-----------------1------------------
tPHLmax+ tsu
It is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to
most advanced CMOS compatible TTL families.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Asynchronous reset
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive edge-triggered clock
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)




nexperia

74LVC161PW Datasheet Preview

74LVC161PW Datasheet

Presettable synchronous 4-bit binary counter

No Preview Available !

Nexperia
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
JESD8-C/JESD36 (2.7 V to 3.6 V)
Specified from 40 C to +85 C and 40 C to +125 C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC161D 40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
74LVC161DB 40 C to +125 C SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
74LVC161PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74LVC161BQ 40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
4. Functional diagram
15
TC
3 D0
Q0 14
4 D1
Q1 13
5 D2
Q2 12
6 D3
Q3 11
9 PE
CEP CET CP MR
7 10 2
1 mna905
Fig 1. Logic symbol
1
R CTR4
9
M1
7
G3
10
G4
2
C2 /1,3,4+
3
1,2D
14
4
13
5
12
6
11
15
4 CT = 15
mna906
Fig 2. IEC logic symbol
74LVC161
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 30 September 2013
© Nexperia B.V. 2017. All rights reserved
2 of 22


Part Number 74LVC161PW
Description Presettable synchronous 4-bit binary counter
Maker nexperia
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