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74LVC1G32-Q100 Datasheet Preview

74LVC1G32-Q100 Datasheet

Single 2-input OR gate

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74LVC1G32-Q100
Single 2-input OR gate
Rev. 4 — 25 January 2019
Product data sheet
1. General description
The 74LVC1G32-Q100 provides one 2-input OR function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V applications.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC1G32GW-Q100 -40 °C to +125 °C
74LVC1G32GV-Q100 -40 °C to +125 °C
74LVC1G32GM-Q100 -40 °C to +125 °C
Name
TSSOP5
SC-74A
XSON6
Description
plastic thin shrink small outline package;
5 leads; body width 1.25 mm
plastic surface-mounted package; 5 leads
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
Version
SOT353-1
SOT753
SOT886




nexperia

74LVC1G32-Q100 Datasheet Preview

74LVC1G32-Q100 Datasheet

Single 2-input OR gate

No Preview Available !

Nexperia
74LVC1G32-Q100
Single 2-input OR gate
4. Marking
Table 2. Marking
Type number
74LVC1G32GW-Q100
74LVC1G32GV-Q100
74LVC1G32GM-Q100
Marking code [1]
VG
V32
VG
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1B
2A
Y4
mna164
Fig. 1. Logic symbol
1 ≥1
2
4
mna165
Fig. 2. IEC logic symbol
B
A
Fig. 3. Logic diagram
Y
mna166
6. Pinning information
6.1. Pinning
74LVC1G32
B1
A2
5 VCC
GND 3
4Y
001aab640
Fig. 4. Pin configuration SOT353-1 (TSSOP5)
and SOT753 (SC-74A)
74LVC1G32
B1
6 VCC
A2
5 n.c.
GND 3
4Y
001aab641
Transparent top view
Fig. 5. Pin configuration SOT886 (XSON6)
6.2. Pin description
Table 3. Pin description
Symbol
Pin
TSSOP5 and SC-74A
B1
A2
GND
3
Y4
n.c. -
VCC
5
XSON6
1
2
3
4
5
6
Description
data input
data input
ground (0 V)
data output
not connected
supply voltage
74LVC1G32_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 January 2019
© Nexperia B.V. 2019. All rights reserved
2 / 12


Part Number 74LVC1G32-Q100
Description Single 2-input OR gate
Maker nexperia
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74LVC1G32-Q100 Datasheet PDF






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