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74LVC1G74GN Datasheet Preview

74LVC1G74GN Datasheet

Single D-type flip-flop

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74LVC1G74
Single D-type flip-flop with set and reset;
positive edge trigger
Rev. 14 — 27 December 2018
Product data sheet
1. General description
The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs,
clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing damaging backflow current through the device when it is powered
down.
The set and reset are asynchronous active LOW inputs and operate independently of the clock
input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition
of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock
transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall
times.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C




nexperia

74LVC1G74GN Datasheet Preview

74LVC1G74GN Datasheet

Single D-type flip-flop

No Preview Available !

Nexperia
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC1G74DP
-40 °C to +125 °C
74LVC1G74DC
-40 °C to +125 °C
74LVC1G74GT
-40 °C to +125 °C
74LVC1G74GF
-40 °C to +125 °C
74LVC1G74GM
-40 °C to +125 °C
74LVC1G74GN
-40 °C to +125 °C
74LVC1G74GS
-40 °C to +125 °C
Name
TSSOP8
VSSOP8
XSON8
XSON8
XQFN8
XSON8
XSON8
Description
Version
plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
plastic extremely thin small outline package;
no leads; 8 terminals; body 1 × 1.95 × 0.5 mm
SOT833-1
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1 × 0.5 mm
SOT1089
plastic, extremely thin quad flat package;
no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm
SOT902-2
extremely thin small outline package; no leads;
8 terminals; body 1.2 × 1.0 × 0.35 mm
SOT1116
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1.0 × 0.35 mm
SOT1203
4. Marking
Table 2. Marking codes
Type number
74LVC1G74DP
74LVC1G74DC
74LVC1G74GT
74LVC1G74GF
74LVC1G74GM
74LVC1G74GN
74LVC1G74GS
Marking code [1]
V74
V74
V74
Y4
V74
Y4
Y4
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
SD
SD
DD
QQ
CP CP
FF
Q
Q
RD
RD
001aah757
Fig. 1. Logic symbol
S
C1
1D
R
001aah758
Fig. 2. IEC logic symbol
74LVC1G74
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 14 — 27 December 2018
© Nexperia B.V. 2018. All rights reserved
2 / 21


Part Number 74LVC1G74GN
Description Single D-type flip-flop
Maker nexperia
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74LVC1G74GN Datasheet PDF






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