74LVC2G00
Dual 2-input NAND gate
Rev. 15 — 3 July 2017
Product data sheet
1 General description
The 74LVC2G00 provides a 2-input NAND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
these devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
2 Features and benefits
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant outputs for interfacing with 5 V logic
• High noise immunity
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8-B/JESD36 (2.7 V to 3.6 V)
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• ESD protection:
– HBM JESD22-A114F exceeds 2 000 V
– MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
3 Ordering information
Table 1. Ordering information
Type number Package
Temperature
range
74LVC2G00DP -40 °C to +125 °C
74LVC2G00DC -40 °C to +125 °C
Name Description
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
Version
SOT505-2
SOT765-1
