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nexperia

74LVC2G16GF Datasheet Preview

74LVC2G16GF Datasheet

Dual buffer gate

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74LVC2G16
Dual buffer gate
Rev. 2 — 12 October 2016
Product data sheet
1. General description
The 74LVC2G16 provides two buffers.
Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.




nexperia

74LVC2G16GF Datasheet Preview

74LVC2G16GF Datasheet

Dual buffer gate

No Preview Available !

Nexperia
74LVC2G16
Dual buffer gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC2G16GW 40 C to +125 C SC-88
74LVC2G16GM 40 C to +125 C XSON6
74LVC2G16GF
40 C to +125 C XSON6
Description
Version
plastic surface-mounted package; 6 leads
SOT363
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
4. Marking
Table 2. Marking
Type number
74LVC2G16GW
74LVC2G16GM
74LVC2G16GF
Marking code[1]
YU
YU
YU
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
 $
< 



 $
< 
PQE
Fig 1. Logic symbol



PQE
Fig 2. IEC logic symbol
6. Pinning information
6.1 Pinning
$
<
DDF
Fig 3. Logic diagram (one gate)
/9&*
$ 
 <
*1' 
 9&&
$ 
 <
DDD
Fig 4. Pin configuration SOT363
/9&*
$ 
 <
*1' 
 9&&
$ 
 <
DDD
7UDQVSDUHQWWRSYLHZ
Fig 5. Pin configuration SOT886 and SOT891
74LVC2G16
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 12 October 2016
© Nexperia B.V. 2017. All rights reserved
2 of 14


Part Number 74LVC2G16GF
Description Dual buffer gate
Maker nexperia
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74LVC2G16GF Datasheet PDF






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