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74LVC373AD Datasheet Preview

74LVC373AD Datasheet

Octal D-type transparent latch

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74LVC373A
Octal D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 4 — 24 August 2020
Product data sheet
1. General description
The 74LVC373A consists of eight D-type transparent latches, featuring separate D-type inputs for
each latch and 3-state true outputs for bus-oriented applications. A latch enable input (pin LE) and
an output enable input (pin OE) are common to all internal latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this condition,
the latches are transparent, that is, a latch output will change each time its corresponding D-input
changes. When pin LE is LOW, the latches store the information that was present at the D-inputs
one set-up time preceding the HIGH-to-LOW transition of pin LE.
When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins Q0 to
Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input pin
OE does not affect the state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied
to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V
applications.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance outputs when VCC = 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C




nexperia

74LVC373AD Datasheet Preview

74LVC373AD Datasheet

Octal D-type transparent latch

No Preview Available !

Nexperia
74LVC373A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC373AD -40 °C to +125 °C SO20
plastic small outline package; 20 leads;
body width 7.5 mm
74LVC373ADB -40 °C to +125 °C SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
74LVC373APW -40 °C to +125 °C
TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
74LVC373ABQ -40 °C to +125 °C
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
4. Functional diagram
18 D7
Q7
19
17 D6
Q6
16
14 D5
Q5
15
13 D4
Q4
12
8
D3
Q3
9
7
D2
Q2
6
4
D1
Q1
5
3
D0
Q0
2
LE OE
mna881
11 1
Fig. 1. Logic symbol
1
EN
11
C1
3 1D
4
7
8
13
14
17
18
Fig. 2. IEC logic symbol
2
5
6
9
12
15
16
19
mna880
74LVC373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 24 August 2020
© Nexperia B.V. 2020. All rights reserved
2 / 17


Part Number 74LVC373AD
Description Octal D-type transparent latch
Maker nexperia
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74LVC373AD Datasheet PDF






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