74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 4 — 24 August 2020
Product data sheet
1. General description
The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The
device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of
their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH
clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either
3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and
5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
2. Features and benefits
• Wide supply voltage range from 1.2 V to 3.6 V
• Overvoltage tolerant inputs to 5.5 V
• CMOS low power dissipation
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• 8-bit positive edge-triggered register
• Independent register and 3-state buffer operation
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-B exceeds 200 V
• CDM JESD22-C101E exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
