8-bit shift register with output register
Rev. 4 — 3 September 2020
Product data sheet
1. General description
The 74LVC594A is an 8-bit serial-in/serial or parallel-out shift register with a storage register.
Separate clock and reset inputs are provided on both shift and storage registers. The device
features a serial input (DS) and a serial output (Q7S) to enable cascading. Data is shifted on the
LOW-to-HIGH transitions of the SHCP input, and the data in the shift register is transferred to the
storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected
together, the shift register will always be one clock pulse ahead of the storage register. A LOW
level on one of the two register reset pins (SHR and STR) will clear the corresponding register.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
2. Features and benefits
• Overvoltage tolerant inputs to 5.5 V
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power dissipation
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Balanced propagation delays
• All inputs have Schmitt-trigger action
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• CDM JESD22-C101E exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
• Serial-to-parallel data conversion
• Remote control holding register